In multifunctional and high-performance electronic apparatuses, a large number of digital signals need to be processed at high speed, and therefore highly integrated system LSIs (Large Scale Integrated Circuits) are mounted. In recent years, there have been developed various memories such as a DDR-SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) with high processing speed that are applicable to such highly integrated system LSIs.
In the electronic apparatuses or the like, the system LSI and the memory are electrically connected to each other on a common board. Hereinafter, the board on which the system LSI and the memory are mounted is referred to as a system board.
Writing data from the system LSI in the memory and reading data from the memory to the system LSI are executed in synchronization with a clock signal. While the data and the clock signal are transmitted through conductor patterns within the system board, a time lag may occur between the data and the clock signal due to various causes. In the foregoing memory that processes a large number of signals at high speed, such a time lag between the data and the clock signal may be a major cause of error occurrences. Therefore, a method for preventing such error occurrences of the memory has conventionally been proposed.
For example, the clock signal and a plurality of delay clock signals (signals obtained by delaying the clock signal) are generated in a memory access circuit described in Patent Document 1. In the memory access circuit, test data is written in the memory in synchronization with the clock signal, and test data is read from the memory in synchronization with the plurality of delay clock signals, respectively. The data written in the memory and the data read from the memory are compared with one another, and an optimum delay value of the clock signal is determined from the result of comparison. This prevents an occurrence of the error in reading the data from the memory.
[Patent Document 1] JP 2005-141725 A